Yes, you are right.
I have a design, which will be synthesised in Xilinx CPLD. Those CPLDs have a global reset.
But now, I need to do a functional simulation of the part of the design.
For the simulation, I am using a testbench, where is the design and some behavioral models (FLASH ROM etc.).
I need to set all FFs in my design to the known state (0) at the start of simulation.¨
In the final hardware implementation, this will be done via global reset.
But how I can do it in simulation ? I browsed the Modelsim manual, but I did not found any command like "reset all FFs to 0".