wire [63:0] r2;
wire [31:0] l_prev;
wire [31:0] r_prev;
wire [55:0] k_prev;
wire [31:0] l_next;
wire [31:0] r_next;
wire [55:0] k_next;
split3 t1( .r0(r_prev), .r1(l_prev), .x(r2) );
PC1 t2( .r(k_prev), .x(k) );
round t3( .l_prev(l_prev), .l_next(l_next), .r_prev(r_prev), .r_next(r_next), .k_prev(k_prev), .k_next(k_next), .i(i) );
initial @ ( posedge clk, posedge req )
begin
if( req == 1 )
begin
m = M;
k = K;
i = 4'b0;
end
end
always @ ( posedge clk, posedge req )
begin
if( i < 4'b1111 | i == 4'b1111 )
begin
i = i + 1;
l_prev = l_next;
r_prev = r_next;
k_prev = k_next;
end
end