ModelSim error: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

[eglantine]

HI,

I'm doing a RAM on vhdl. I can compile but when I try the simulation I've this message :

Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

I've already done : NumericStdNoWarnings = 1 in modelsim.ini as it has been said in others topics.

I'm really not an expert on VHDL and modelsim. I give you my code, maybe it can help you to help me.

Thank you very much



***********************RAM************************

use IEEE.Numeric_Std.all;

entity sync_ram is
  port (
    clock   : in  std_logic;
    we      : in  std_logic;
    address : in  std_logic_vector;
    datain  : in  std_logic_vector;
    dataout : out std_logic_vector
  );
end entity sync_ram;

architecture RTL of sync_ram is

   type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
   signal ram : ram_type;
   signal read_address : std_logic_vector(address'range);

begin

  RamProc: process(clock) is

  begin
    if rising_edge(clock) then
      if we = '1' then --ecriture
        ram(to_integer(unsigned(address))) <= datain;
      end if;
      read_address <= address;
    end if;
  end process RamProc;

  dataout <= ram(to_integer(unsigned(read_address)));

end architecture RTL;

**************RAM_TB******************

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;

entity Ram_TB is
end entity Ram_TB;

architecture Bench of Ram_TB is

  signal Address :Std_logic_vector(9 downto 0);
  signal DataIn, DataOut :Std_logic_vector(15 downto 0);
  signal WE : Std_logic;
  signal clock : Std_logic;
  signal StopClock : boolean := FALSE;

  component sync_ram is 
  port (
    clock   : in  std_logic;
    we      : in  std_logic;
    address : in  std_logic_vector;
    datain  : in  std_logic_vector;
    dataout : out std_logic_vector
  );
 end component;
   
begin
    
  UUT: entity work.sync_ram(RTL)
  port map (
    clock   => clock,
    we      => WE,
    address => Address,
    datain  => DataIn,
    DataOut => DataOut
  );

  ClockGen: process is
  begin
    while not StopClock loop
      clock <= '0';
      wait for 5 ns;
      clock <= '1';
      wait for 5 ns;
    end loop;
    wait;
  end process ClockGen;

  Stim: process is

  begin

    wait until rising_edge(clock); -- cycle 1
    datain <=    "0111111100000001";
    address <= "0000000001";
    we <= '0';

    wait until rising_edge(clock); -- cycle 2
    we <= '1';
    datain <= "0000010011000011";

    wait until rising_edge(clock); -- cycle 3
    datain <=    "0000011100110001";
    address <= "0000000010";

    wait until rising_edge(clock); -- cycle 4
    we <= '0';

    wait until rising_edge(clock); -- cycle 5
    address <= "0000000001";

    wait until rising_edge(clock); -- cycle 6
    address <= "0000000010";

    wait until rising_edge(clock); -- cycle 7
    wait until rising_edge(clock); -- cycle 8

    StopClock <= true;
    wait;
  end process;

end architecture Bench;

 

[devas]

array std_logic_vector modelsim

Hi,

You should initialize the signal read_address, e.g.
signal read_address : std_logic_vector(address'range) := (others => '0');

At time 0 ns, Modelsim executes the line:
dataout <= ram(to_integer(unsigned(read_address)));

At that moment read_address is "UUUUUUUUUU" and that is the reason Modelsim returns the warning message.

Devas