modelsim compiling .vhd into library to use with verilog

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meir

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I'm compiling .vhd files into a library using
vcom -work util_library util_module.vhd
I'm trying to use this library with verilog cobe. i.e. :
vsim work.tb.v -L util_library
but the simulator doesn't seem to search the library or I get the modelsim can't compile 2 HDL languages error.
Ant ideas ?
Thanks
 

Your modelsim.ini should indicate where to find the library, library_name= <path>
 

It does. i.e I have in the .ini file xilinxcorelib = xilinxcorelib.
but for some reason it doesn't seem that the simulator is searching this library:
The problem could be that I'm trying to compile the xilinx files using the modelsim downloaded from ALTERA website !?
because I also get the ERROR :

# ALTERA version supports only a single HDL
# ** Fatal: (vsim-3039) C:/Users/meir/Desktop/tvs/ise/ipcore_dir/fifo_segment/fifo_segment.v(483): Instantiation of 'FIFO_GENERATOR_V9_3' failed.
# Time: 0 ps Iteration: 0 Instance: /try_tb/com_top_inst/rx_fifo_segment_inst File: C:/Users/meir/Desktop/tvs/ise/ipcore_dir/fifo_segment/fifo_segment.v
# FATAL ERROR while loading design
# Error loading design
is there a solution ?
PLZ HELP

** Error: (vsim-3033) C:/Users/meir/Desktop/tvs/ise/ipcore_dir/fifo_segment/fifo_segment.v(483): Instantiation of 'FIFO_GENERATOR_V9_3' failed. The design unit was not found.
#
# Region: /try_tb/com_top_inst/rx_fifo_segment_inst
# Searched libraries:
# C:/Users/meir/Desktop/tvs/modelsim/work
 
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