modelsim and system verilog question

I get different behavior depending on how I define a clock divider so I wrote some test code. I'm using modelsim-altera 10.0c. Here is the code.

always @(posedge clk or negedge reset_n)
if (~reset_n)
begin
aclk_div <= 0; // 2 bit counter
bclk_div <= 0; // 2 bit counter
end
else
begin
aclk_div <= aclk_div + 2'h1;
bclk_div++;
end



always @(posedge clk or negedge reset_n)
if (~reset_n)
acount <= 0; // 8 bit counter
else if (aclk_div == 2'h3)
acount <= acount + 8'h1;



always @(posedge clk or negedge reset_n)
if (~reset_n)
bcount <= 0; // 8 bit counter
else if (bclk_div == 2'h3)
bcount <= bcount + 8'h1;


I would expect the behavior of acount and bcount to be identical. However, acount transitions at the clock edge when aclk_div == 3 (which I think is correct) and bcount transitions on the clock edge when bclk_div ==2.



Any thoughts?

you have a race

Use

bclk_div <= bclk_div + 1;

instead of

bclk_div++;

All of the ++/--, etc. operators are blocking assignments.