thank you,
do you know why I get
# Error: ELAB1_0021: filename.vhd : (lines, 0): Types do not match for port "some_port".
Aldec FAQ says:
If you are receiving this error, please check which standard you are using when compiling your files. If you are using different standards for different files, (e.g. 2002 and 2008) this error can occur. You will need to compile your files using the same standard.
But I don't understand what it means, like i looked for on tool>perferences and it shows VHDL compiler- standard version- VHDL 1076-2002. But this is the setting I am using for compiling all the vhd files in my project. so the possible reason- "different standards for different files" would not apply to me! or is it?
Thanks