modelling two-phase clock in Cadence RC

[sabkumar.r]

Hi,
My design requires two clocks. One clock which has a 90 degree phase shift with respect to the other (but with same frequency). During synthesis (with cadence RC) I defined the first clock as follows:

create_clock -name clk1 -period 1000 clk

Now how do i specify the phase shift for the second clock?

thanks in advance,
sabareesh

 

[AdvaRes]

Create a delayed version of CLK1 with a delay of 1/4 th the period of CLK1

 

[sabkumar.r]

Create a delayed version of CLK1 with a delay of 1/4 th the period of CLK1

Can you please explain how to do that?