Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Modeling Jitter in PLL-based Frequency Synthesizers

Status
Not open for further replies.
M

mustangyhz

Member level 5
Member level 5
Joined
Nov 18, 2008
Messages
87
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,978
Does anybody download "Modeling Jitter in PLL-based Frequency Synthesizers" from www.designers-guide.org and test it in cadence?
How to simulate it? can you send me the project in cadence? thanks!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top