Modeling Faults with VHDL language

[lahrach]

how to model faults like stuck-at 1 (0) using VHDL,

friendly,

 

[FvM]

I fear, it's not quite clear waht your asking for. "Stuck at" normally happens, if a logic driven output never changes it's state, possibly to a logic design error, or just intentionally. If it it's not by intention, what do you want to simulate? You have to analyze the logic and find out, why the output takes the same state under all conditions.

 

[lahrach]

stuck-at 1/0 means that the output is always at 1/0 whatever the inputs,

regards

 

[TrickyDicky]

easy:

output <= '1';

 

[wsong0210]

In Verilog it is possible to set a wire to a value in test bench on the fly.
Such as you have a wire "sig" in a module called DUT
in test bench you can write
assign DUT = 1;
to cause it to one.

Seems VHDL does not support this.

 

[Dave_PL]

Try 'force'.

 

[Alexium]

Try 'force'.

Also Verilog only.

 

[Dave_PL]

No. 'Force' and 'release' are in VHDL2k8 standard.

Usage:
signal <= force illegal_state;
signal <= release;

You can do that also with ports but then you have to use 'force in/out'

 

[Alexium]

Oops, sorry, haven't got a chance to study 2k8 yet