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Model parasitic effect in transistor in SIMetrix (spice)

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Hi,
I´m trying to model the real performance of a transistor in a SPICE programm (SIMetrix). I´ve noticed that the model I´ve downloded has modelled the parasitic inductances and resistances, so I´ve tried to delete them (only the inductances) from the .lib file and place them in the circuit to get such a equivalent circuit but it doesn´t work well. Then I read in the .lib file that the inductances have some dependency on the transconductance. For example, Lg is the parasitic inductance in the gate so the line is "Lg gate g1 {Lg*if(dgfs==99,0,1)} " where dgfs is refered somehow to the transconductance. So I don´t know if I have to model an equivalent circuit for the transconductance or simply I´m missing something.

The transistor model is ISC030N10NM6 from Infineon.

Hope someone can help me!
 

RF transistor models will try to incorporate whatever L is within the
extents of the physical device. If you're not playing within a couple
decades of fmax, you can probably do as you please. The "dgfs"
blah-blah is a logical enable of the Lg term and you could make
that a hard coded "0" or "1" or just do as you like with the whole
inductor.

A real packaged RF transistor has real bond wire and lead-length
inductances.
 

And how can I model that term dgfs like a component in the circuit? The idea is to delete manually this components in the .lib file and to replicate this scheme in spice.
1688392012575.png



Thanks
 

dgfs is an "all or nothing" flag variable, that makes the gate
inductor have zero (bad idea, that) or =Lg (where Lg is a
parameter from elsewhere, through the argument chain).
You want it or you don't.

I suggest that you create two model branches, one with and
one without the close-in inductors, run a circuit you care
about high frequency on, and see if there is a meaningful
difference in anything that matters.

In my opinion a lot of this here, is really for RFIC on chip
signal chain accuracy at very high (GHz) frequencies. If
this is not your application, then you could gain solution
time without costing accuracy by either deleting / rewiring
or making trivial values (if you don't want to get into changing
subcircuit topology, and can stand the solution cost of those
useless baggages).

But if you want to operate within a decade or two of process
fmax you probably want those parasitic elements kept around,
at least in a "max challenge" model branch, so you can be
sure you've got the mojo you think.
 

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