model card : simple resistor. Warning : select vamod for 'resistorcustom'

[pierre13]

Hello,

I am defining a model card for a simple custom resistor : deltaV=R*I targetting a simulation in HSIM (Fast Spice simulator "coming from Hspice").
When I launch the simulation of my netlist : a circuit including this simple resistor custom, I have a Warning message.

My goal is to evaluate the runtime (and accuracy) impact of the model card strategy in comparison with a resistor from analogLib, and with a simple .hdl inclusion of the verilogA model of the simple custom resistor in the circuit netlist.

Warning message :

Reading (pass #2) '/home/.../resistorCustom_model_mc/resistorcustom_corners.lib' (.lib typ)
Reading (pass #2) '/home/.../resistorCustom_model_mc/resistorcustom_corners.lib' (.lib value)
Reading (pass #2) '/home/.../resistorCustom_model_mc/resistorcustom_corners.lib' (.lib model_core)
Warning: file
'/home/.../resistorCustom_model_mc/resistorcustom_corners.lib'
line 30-31: select vamod for 'resistorcustom'
--> x1 pin1 pin2 _resistorcustomM R=Resvalue


The model card startegy is the following :

resistorcustom_model.va :
`include "constants.vams"
`include "disciplines.vams"

module resistorcustom(t1, t2);
inout t1, t2;
electrical t1, t2;

parameter real R= 5e03;

analog begin

I(t1,t2) <+ (1/R)*V(t1,t2);

end
endmodule

• resistorcustom_corners.lib :

** Corners definitions
.LIB TYP
.LIB "resistorcustom_corners.lib" VALUE
.LIB "resistorcustom_corners.lib" MODEL_CORE
.ENDL TYP



.LIB VALUE

.HDL '/home/.../resistorCustom_model_mc/resistorcustom_model.va'

.ENDL VALUE


.LIB MODEL_CORE

.SUBCKT _resistorcustom pin1 pin2
x1 pin1 pin2 _resistorcustomM R=Resvalue

.MODEL _resistorcustomM resistorcustom

.ENDS

.ENDL MODEL_CORE

• Instanciation in the circuits netlist (extract) :

...
.PARAM rvaluebitcell=1000
...
.LIB "/home/.../resistorcustom_corners.lib" TYP
...
.subckt pe26_1x1_Ranalog bl sl vpw wl
x_rbitcell bl net1 _resistorcustom R=rvaluebitcell
xm1 net1 wl sl vpw nlvtlp w=100e-3 l=100e-3 nfing=1 mult=1 srcefirst=1 mismatch=1 lpe=0 numcos=1 numcod=1 ngcon=1
.ends pe26_1x1_Ranalog


Regarding the runtime and accuracy, i noticed :
from "resistor analogLib" to "verilogA inclusion in the netlist of the simple model resistor" : very very slight increase in runtime and change of results accuracy (some few seconds and few mV)
from "verilogA inclusion in the netlist or the simple modle resistor" to "model card startegy" : moving from 2mn runtime to 40minutes, and some DC and dynamic waveforms are different (env. 100mV).

Thanks to help me with the warning message and the "select vamod" point.

P.