Dear Alosevskoy,
Apologies for the late reply. I guess you already completed the design, if not here is my answer:
From the log file you've shared the problem seems to be pins that are not created in verilog file.
1. For signal pins you need to have pins for Smod pins inside the verilog file, to match the pins in def file.
- In your situation, there seems to be a discrepancy between def file & verilog file. For example for the line "**WARN: (ENCDF-244): Pin 'c_a' is not created because it's not in the netlist and also not a P/G pin.", it says that "c_a" pin does not exists in verilog, and also it is not declared as a power pin in P&R tool. YOu either need to declare it as a power pin (if it is so), or add it to verilog.
2. For power pins, you don't need to have them in verilog. YOu can directly create them in place and route tool.
I hope it helps,
BR,
Gökhan
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