misunderstanding vhdl process?

[Reissner]

Hope the following code snipped is not too small.

  myVJtagInstance : MyVJtag port map (
    ir_out => ir_outB,
    ir_in  => ir_inB,
    tdi => tdiB,
    tdo => tdo,
    tck => tck,
--    tms => tms,
--    virtual_state_cdr  => led(0),
--    virtual_state_cir  => led(1),
--    virtual_state_e1dr => led(2),//0
--    virtual_state_e2dr => led(3),
--    virtual_state_pdr  => led(4),
    virtual_state_sdr  => sdr--led(5),//0
--    virtual_state_udr  => led(6),
--    virtual_state_uir  => led(7)
    );

load1 <= ir_inB(0) and not(ir_inB(1));
  --load2 <= ir_inB(1) and not(ir_inB(0));
  --comp  <= not(ir_inB(1)) and not(ir_inB(1));
  --store <= ir_inB(0) and ir_inB(0);

  --statusOk <= tdi='1' or tdi='0';

  readArg1 : process (tck)
    begin
      if rising_edge(tck) then 
        if load1='1' and sdr = '1' then 
          arg1(7 downto 1) <= arg1(6 downto 0);
          arg1(0) <= '1';--tdiB; -- shift
        end if;
      end if;
    end process readArg1;

 led <= std_logic_vector(arg1);

the intention was to read in arg1 sequentially from tdiB via a shift.
Since this did not work,
I shifted in 1's only.
The strange thing is, that now arg1 is all 1 --- even shortly after reconfiguration.
I can see this because arg1 is connected to leds.

I would have expected that arg1 remains as is until tck has a rising edge and ....
But As far as i see, i have full control over tck and send no signal.

How can i explain myself the behavior of all 1??
Any ideas very much appreciated.

 

[TrickyDicky]

You question is not very clear. Whats the problem?
And please dont post commented out code - it adds to confusion.

 

[Reissner]

ok sorry for commenting out code and not being clear.

The code above actually sets led's on my board (signal led).
Since led is connected to arg1, i can read off arg1 from the leds.

My idea is to shift arg1 in with tck (jtag test clock).
The strange thing is, that all leds are on, even if i do not toggle tck.
So it looks as if the process runs without waiting for tck.

 

[FvM]

It might be that arg1 is initialized to all '1', e.g. if "initial value don't care" is set.
I'm also not sure if the virtual TCK is not toggled before accessing the VJTAG instance explicitely.