Hi,
I have checked the extracted view of my layout design, there aren't any errors available or atlease there isn't any description about my layout design. I don't know why , eventhough I have used the same resistors in my layout design,that I have used in my schematic design, I am getting errors during my LVS. Because of this, I am getting other descrepancies like missing net due to the missing resistance instances in my layout design. Please help me out to solve this issue.Thanks in advance.