As you never stated what device you are using (other than it being Xilinx, i.e. ISE XST). Assuming the fastest speed grade (-3) of Virtex 7 the regional clock buffer (BUFR) maxes out at 600 MHz, the horizontal clock buffers max out at 741 MHz, and the global clock buffers max out at 741 MHz. So the top end device that can use ISE XST doesn't even have the capability to clock at that frequency. And forget about Spartan 6 the frequencies are much lower than that.
Now you might be able to do this in a Virtex Ultrascale part (Vivado) as it's maximum clock frequency for the clock networks is 850 MHz in the 1.0V -3 speed grade part. But expect to pay a huge premium for the parts, they aren't cheep.
If you made the decision to implement this in an FPGA, then you made the wrong decision and didn't do the due diligence necessary to ensure a successful design. I would go the the manager of the project and let them know you screwed up and it can't be done.
Now I could suggest something like using a 200 MHz clock and producing 0, 90, 180, 270 degree phase shifted versions of the clock and using four counters each of them on one of those clock domains, which you then sample the other three counters on each clock domain. You would then have to figure out if that can give you enough information to obtain the resolution you want and how you would use the information. Things like deciding which phase has the correct information may require large amounts of redundant logic running on all four clock domains, until there is some way to determine which clock domain has the "correct" value. Given your abilities (not know you should do STA on a design, not knowing how to write constraints, not knowing what is in the data sheet and DC/AC switching characteristics) I would strongly suggest NOT doing the above, as you will need to fully understand the items mentioned. Even as a highly experienced professional I would be hesitant to commit to doing a design like this as it's likely to bite me in the rear and result in my having to work long nights and weekends trying to fix it when it starts to misbehave right before we start shipping units to customers.