nawaz.mjcet
Newbie level 6
Hi all,
In formality while debugging using schematics, i'm getting mismatches at input of flip flops(for example 1 at input of implementation flop and 0 at the input of reference flop).But the output is same for both the flops.so what setup modifications should be done in order to pass the verification.
Thanks in advance.
Regards,
-Nawaz.
In formality while debugging using schematics, i'm getting mismatches at input of flip flops(for example 1 at input of implementation flop and 0 at the input of reference flop).But the output is same for both the flops.so what setup modifications should be done in order to pass the verification.
Thanks in advance.
Regards,
-Nawaz.