Apr 18, 2015 #1 P punu Newbie level 1 Joined Apr 18, 2015 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 6 I am not able to resolve the following DRC error in a UMC65 design. L2.D Minimum L2 density cross full chip is 10% What is L2?
I am not able to resolve the following DRC error in a UMC65 design. L2.D Minimum L2 density cross full chip is 10% What is L2?
Apr 18, 2015 #2 deepsetan Advanced Member level 4 Joined May 8, 2013 Messages 119 Helped 6 Reputation 12 Reaction score 5 Trophy points 1,298 Location Malaysia Activity points 2,137 punu said: I am not able to resolve the following DRC error in a UMC65 design. L2.D Minimum L2 density cross full chip is 10% What is L2? Click to expand... Hi, Maybe you can check this thread https://www.edaboard.com/threads/95896/
punu said: I am not able to resolve the following DRC error in a UMC65 design. L2.D Minimum L2 density cross full chip is 10% What is L2? Click to expand... Hi, Maybe you can check this thread https://www.edaboard.com/threads/95896/
Apr 18, 2015 #3 erikl Super Moderator Staff member Joined Sep 9, 2008 Messages 8,108 Helped 2,695 Reputation 5,370 Reaction score 2,305 Trophy points 1,393 Location Germany Activity points 44,123 punu said: What is L2? Click to expand... Find the layer in the LSW; the assignment to the layout can be found if you toggle it invisible - visible, s. here: View attachment LSW-description.pdf Or search your PDK docu for L2.
punu said: What is L2? Click to expand... Find the layer in the LSW; the assignment to the layout can be found if you toggle it invisible - visible, s. here: View attachment LSW-description.pdf Or search your PDK docu for L2.