Well, that depends on the application .For digital circuits ,for example, it is usually required to reduce the drain capacitance because the drain node is usually connected to output while the source is usually connected to GND or Vdd .Thus, by decreasing the drain capacitance, less delay ad power consumption can be achieved .
For analog applications, I believe you should check the node where the pole is required to be reduced and reduce its capacitance .It may also include a compromise and optimization as you may encounter Miller multiplication for example .