standard length of analog mosfets
(1) Process variation can affect everything from poly-Si interconnect (a problem getting more significant with deep sub-micron) to gate length. Not just minimum gate length MOS.
In fact, it is a very important factor for mixed RF-analog-digital IC design.
This is because RC increases with deeper sub poly-Si (due to smaller cross-sectional area), despite vertical traces are used to reduce this effect. RC of poly-Si affects the S-parameters!
(2) You need to check the transistor model used for your RF circuit simulation. You should be able to check it in your designer's manual, say if you are using Cadence SpectreRF or HP-ADS. Usually HSpice models.
Some design houses use their own models compatible to foundries.
For example, some foundries even provide Cadence compatible transistor models for different substrates, process tolerance, etc.
You also need to check the substrate you use. There are several substrates used for RF that confines the models you will use to accurately predict the performance and LO leakage (a problem always with Mixer design).
It is strange to see linearity decreases with increasing Rds (for wider gate length found in older cmos processes such as 0.25 and 0.35, which produce better RF-analog circuits than today's 0.18 and 0.13)
I have been using UMC, if not TSMC or SMIC. They have very good models and support.
If you are using CSM, I don't think they are good. They don't provide system and circuit design level support.