Hi
i hope you are doing well
I am using MIMCap_MML130E in umc130nm technology for first time and i don't now how to connect the terminal and what layers should i use what vias ?
I attached below a multiplier
Thanks in advance
First, you should check with your technology design rule manual, it should explain the layer names, purposes, etc.
Usually, the MIM capacitor layers are placed between regular Mx and My (y=x+1), and a via between Mx and My is also used for connecting the top metal (My) with both the bottom plate layer and the top plate layer.
No, AL_RDL (Aluminum redistribution) is the topmost layer, all on-chip metal layers should be below it.
I never seen that MIM layers are connected to AL_RDL.
Usually MIM plate layers are called CBM / CTM or like that.
Check your ITF file if you are using StarRC (should be located right next to NXTGRD file - which location you can see in StarRC command file or in SPF file), or ICT file / layer_setup file if you are using QRC.
If you tell me what extraction tool / flow you are using, I may be able to give more specific suggestions on how to find the MIM layer names.
Or, check with your DRM.
i used calibare tool (mentor) on cadence virtuoso
i am taking about metal layer which capacitor was built from. AL_RDL.
i can remove all layers except single layer (capacitor layer) i found it AL_RDL
if you use cadence you will find in via >>stack >>from metal A to metal B
choose metal A: AL_RDL metal B: any layer you want to connect your lines
I find it very strange that MIM capacitor uses layer AL_RDL (by the way, MIM capacitor should use two layers - not one),
but if you think you are doing it right, and happy with that - be that.