[SOLVED] MIG Hierarchy issue(Virtex-7)

[rahdirs]

Hi,

In the design hierarchy mentioned in ug 586 about the simulation top file of example design,he has sub-modules of user_ design_top & memc_ui_top.(Attached snapshot).

But in the example design,i generate these are not even in the project.I added them & do i even need to instantiate them into my example_top?(Attached is my hierarchy snapshot)

 

[ads-ee]

Those little + signs next to the module names...you should click on them and open up the entire hierarchy and post that picture.

I suspect you have something missing in your project under the example_top file as there are all those miscellaneous (IP core) files at the same level as your example_top.

 

[rahdirs]

Hi,

@ads-ee

Will upload a better picture,with all the modules opened up.(They are just sub-modules.)

They are not ip core files.An ip core file is usually a .xci file,while all those files are .vhd or .v files.Refer to the second figure,you'll get an idea about those module's names.

 

[ads-ee]

They are not ip core files.An ip core file is usually a .xci file,while all those files are .vhd or .v files. Refer to the second figure,you'll get an idea about those module's names.

Sorry about trying to help you with my inferior knowledge of MIG simulation. I guess using it in a dozen designs and running simulations on those designs doesn't count for anything.

I certainly never knew you could run a functional simulation with an .xci file, you know more about running a simulation on the MIG example design than I do, so I will bow to your expertise on the matter.

Regards

 

[rahdirs]

Hi,

@ads-ee: was that sarcasm ?

Anyway,my problem is solved:
http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-Hierarchy-issue/td-p/571330