[SOLVED] MIG FIFO Requirement

pcmistic · Mar 18, 2017

Hi, I'm quite newbie in Verilog and FPGAs. I'm trying to access the DDR2 SDRAM on my FPGA board (Opal Kelly XEM6310-LX45). I instantiated RAM controller module which i generated with MIG tool in ISE. Now I'm trying to control the interface. I have read UG388 but there is a point that I'm confusing. Does MIG module have Write, Read and Command FIFOs internally, or do I add these FIFOs to MIG externally?

dpaul · Mar 18, 2017

I have never used the DDR2 MIG IP core, but as I understand it from Pg16, ug388.pdf, from the block diagram I see that internally it has command (CMD FIFO *) and data FIFOs (32 bit bi-/uni-drectional).
Then I have this excerpt...
FIFOs are used at the User Interface of the command path and datapath to queue up memory requests and to manage the transfer from the user clock domain to the memory controller clock domain.

As I understand it, it means that FIFOs exist just immediately after the user interface ports inside the MIG core.

pcmistic · Mar 19, 2017

Thank you dpaul.

[SOLVED] MIG FIFO Requirement

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[SOLVED] MIG FIFO Requirement

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