I don't understand how people are able to simulate their user designs.
I've tried to simulate without the model, because I have no idea how to include it in Vivado simulator.
App_rdy never goes high and although the MIG finishes initializing, all the DDR stuff does nothing.
Thanks for your time.
You go to Micron's web site, find a compatible DDR part and download the verilog/VHDL simulation model. Not sure why that is a problem. Once you have that you instantiate it in the testbench and run the simulation. Nothing happens because you have to have a DDR model to run the simulation, it requires the DDR RAM to exist in the testbench to read and write to perform calibration.
Is it you don't have a testbench? don't know how to instantiate? don't know know how to compile/add files for the simulation?
It's obvious you don't know how to script the simulation yourself, relying on the GUI to do it is useless for understanding how to do stuff, IMO. In a Vivado Tcl shell use the following commands:
use xvlog/xvhdl command to compile each file of your design
xvlog <module_file_name>.v
xvhdl <entity_file_name>.vhd
for a verilog simulation (_ver: not all libraries are necessary only the ones you need)
xelab -debug typical -timescale 1ns/1ps -L work -L unisims_ver -L unimacro_ver -L xilinxcorelib_ver -L secureip <module_file_name>
run the simulation in GUI mode, without the -gui you'll run in command line mode
xsim -gui <module_file_name>
If you absolutely must use the GUI.
Add the testbench and the DDR model and any other models you might have to the source code by adding with simulation only selected uncheck the for synthesis option.