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MIG, DDR2 and Virtex5 - tutorial or ise example

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Feb 24, 2004
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MIG, DDR2 and Virtex5


can someone who has used Xilinx's MIG DDR2 controller help?
i am trying to generate and simulate the DDR2 controller with memory
MT47H16M16 memory model generated by MIG 2.0 (Xilinx ISE 10.1
> SP3)

If someone has a tutorial or ise example.

thanks in advance

I don't know the memory you are using, but I used it many times without any problems.

It creates the whole memory controller, testbenches and simulation date for you so you just need to analyze the simulation after it is done.

What is it you want to know?

Best regards,
/Farhad Abdolian


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thanks farhada for your response.

It s easy to generate core with MIG but the question how to simulate or how to instantiate this core in your card how to verify if data is correctly written in DDR2.


i use this design board for test:

part number AVNET: AES-V5FXT-EVL30-G
Xilinx Virtex-5 XC5VFX30T-FF665 FPGA

HI Sorry for the delay, having problem with my old PC and finally ordered a new one!

When you create a new project in MIG, it creates a simulation directory for you, in that directory, you can run the sim.exe file which will create a WLF file fro you. You can study the simulation by loading the WLF file into ModelSim.

There are many applications notes from Xilinx that describes the DDR2 iimplementation using MIG, one such is XAPP458 that I used previously. It is not for your device, but will give you good feeling about how you can implement it.

I can give you more help after I receive my new PC and installed ISE on it, but right now, I do not have access to Xilinx tools.

Best regards,

Hi Farad
I have the same problem with MIG cause I'm new to it.
Will you please give me your e-mail address then I can ask you my questions while doing my project. It will be generous of you.
Thanks in advance

That post was more than a year ago, so you are probably better of posting in the thread.

Did you read XAPP458 yet? What are the specific problems you run into?

Hi there
Thank you for your reply. I'm using Virtex5 FPGA for RAM controlling. I have problem with adjusting ucf and implementing my design. Can you introduce a good source to me in order to become familiar with the process?
Thanks in advance

Thank you so much.
I', now following the procedure. But it seems that I can't use use ChipScope with systems where the program is running out of DDR/DDR2. Theres seems to be erros with runing vio files using MIG for DDR2. Do you have any solution or any other source which helps me find which changes should I make in the source code?

It seems that I can not use "vio" type names with virtex5. One of the erros is "'vio_sync_out32' is not supported in target 'virtex5'. " :(

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