Ok knark...things clearer now,yet you don't clarify if the amplifying stage is fully-differential or not.In case it is you need a CMFB to stabilize your common mode output potential (you can use an ideal model initially for your simulations and see how things work).
Start from the fact that your DC output must be set to Vdd/2.Then try to size your transistors,find bias current and bias voltages according to your specifications.
I would suggest that you leave hand calculations at the edge and try with simulations (trial and error as you said).
Apparently if you change the Vout,DC from the point that is now to a new point of Vdd/2,your circuit performance will change...Thus you need to do redesign to bring it back to a desired status.
Remember that in analog design you must make compromises among the various specifications you have to achieve.You lower the one,increasing the other etc...until you catch them all!