bismillah,
How’s it goin’ brother. Your interface problem is a twofold one. On one side, you need to develop a VHDL core to interface with your microprocessor. On the other side, you need to write C/assembly subroutines to interface with your FPGA. I don’t imagine that there are a readily developed code out there that well suit your requirements for two reasons. Firstly your interface is dependent on the specific kind of peripheral you’ll be using on the microprocessor side which I recommend to be a parallel port with DMA transfer capability if possible. Secondly, you might find some codes out there which you hardly can understand a word from. Usually, coherent designs are developed using device macros and attributes (not behaviourally) which as you know differ largely from one vendor to another. So my advice to you is to quite searching and commence work immediately.
General guidelines for your design are as follows:
- Try to come up with an interface which is as modular as possible. You might be able to elaborate largely on things with this regard as your “abstraction layer” can be as complex as you choose to be, encapsulating sophisticated commands and requests between your FPGA and uP.
- Don’t forget to synchronize your signals of course.
- Use two ported RAM blocks if possible as read/write buffers. Xilinx has got some nice asynchronous FIFOs readily there for your usage.
- Of course, your core should be two-sided as to facilitate modularity.
Hope this is beneficial to you.
Cheers.