Hi tachyons,
we need to have
1. Synthesized RTL netlist
2. SDC
3. Data setup and Design planning completed.
4. Hard macros placed and fixed
After floorplanning we check for issues such as
1.Cells placed in “hard placement blockage” areas
2. Metal layer inconsistencies against the library
3. R/Cs for routing layers
4. Narrow placement regions (“chimneys”)
5. Legal sites for cell placement
6. Large RC variations between metal layers
we also perform ZIC analysis that our SDC is not overconstraiing(unrealistic) the design
cheers