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Methods to read the bit file after was burned in to FPGA

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Jun 4, 2012
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I made a board with a FPGA Kintex 7 configurated in JTAG-Mode (no external memory for configuration). Because the board will be tested in a nasty enviorement, I want to know if I can read the configuration file back from FPGA after I burn it with Impact tool? Because I want to compare it with the bit file generated by compiler? We want to see if durring the tests, the configuration from inside of FPGA have some changes, regarding to the default.


As long as you don't disable readback of the device in your bit file IMPACT can perform a verify on the device.

You could also use the FRAME_ECCE2 and/or the SEM IP (which I don't think is free). The FRAME_ECC can be setup to scan the configuration frames for single bit errors. Read the 7 Series configuration user guide for information on using the FRAME_ECCE2 primitive. This means you'll have to have something setup to monitor the FRAME_ECCE2 outputs.

I'm assuming your "nasty environment" testing is radiation testing of some kind as the likelihood of bit flips occurring is very low otherwise.

Thank you for answers, I am trying to do some readback test using Impact on a nexys 3 board, but until now i cannot find in Impact where is the commad to set that.

My kintex-7 board has no external memory for configuration, is that a problem for readback, or it will work just fine?

If readback is not disabled, impact and readback and compare your bit file

Hello to all,

I made all settings I found on the internet, but i can't do readback on a Nexys 3 board with Spartan (I don't have the Kintex 7 board at mine now), but I don't see the Readback option. What I am missing?

Thank you!


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There isn't a specific readback the configuration memory to a file on the computer if that is what you are looking for. You can perform that type of readback but you will have to create a custom JTAG xsvf to do it. Or use something connected to the SelectMAP to read the configuration memory to some device (like a UART).

The Verify checks the configuration memory for errors.

The readback data files in the Readback Options is used if you command a readback over JTAG or SelectMAP and capture the data with something. You can't use the original bit file as there are some things that shouldn't be checked like RAM blocks.

I think you're going about this wrong. If you want to test this in a radiation beam then you should have had another device connected to the SelectMAP and done all the readbacks over that and sent the data up to a computer over a USB 3.0 link for comparison. I think doing this over JTAG the standard manual JTAG readback/verify operation is too slow.


Yes I already tested that option "Verify", works well. I need the content of memory because i want to make a script to compare the readback file generated by compiler and the readback file readed from FPGA, but I think is enought what Impact doing with that option "Verify".
But look this, I found some pictures over the google, where apper the "Readback" option, how was activated? they made a custom JTAG xsvf?
So, if I understand right for correcting in real time the configuration file from errors durring exposure at beam I need something faster than JTAG.

Ps: but I think readback option is only for flash memory..


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I have done the verify step for Kintex-7. But I have a question: during the tests if the configuration file has changed (because of SEUs) and I verify the configuration file via JTAG with Impact and "verify function", the number of differences (350700 from attached image) can be named as SEUs? Because those are some differences but I don't know how to interpret that number.

PS: We are interested to do some verify and scrubbing tasks only via JTAG, in our design we can use SelectMap interface.


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You can generate a .msk (mask) file. This can be used to determine what parts of the readback data can be compared to the bit file.

Yes I do that, I want to know if that number of differences can be the number of Upsets in configuration memory.

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