-100 5 500
-27 44 -99
100 200 -300
reading_from_file : process (clk) is
file my_file : integer open read_mode is "C:\some_location\some_file" ;
...
FILE declaration must have a subtype indication that is a file type.
signal incoming_pixel : integer ;
signal pixel_out : integer ;
reading_from_file : process ( clock ) is
file text_file : text open read_mode is "C:\location\some_text_file.txt" ;
variable current_line : line ;
variable incoming_pixel : integer ;
begin
if ( not endfile ( my_file ) ) then
if rising_edge ( stimulus_in_clock ) then
readline ( my_file , current_line ) ;
read ( current_line , incoming_pixel ) ;
end if ;
end if ;
pixel_out <= incoming_pixel ;
end process reading_from_file ;
This is what I'd like to do.You will need to either do multiple reads per line
readline ( my_file , current_line ) ;
read ( current_line , incoming_pixel1 ) ;
read ( current_line , incoming_pixel2 ) ;
read ( current_line , incoming_pixel3 ) ;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 reading_from_file : process ( clock ) is file text_file : text open read_mode is "C:\location\some_text_file.txt" ; variable current_line : line ; variable incoming_pixel : integer ; variable pel_cnt : integer := 0; begin if rising_edge ( stimulus_in_clock ) then if ( not endfile ( my_file ) ) then if pel_cnt = 0 then readline ( my_file , current_line ) ; end if; read ( current_line , incoming_pixel ) ; pel_cnt := (pel_cnt + 1) rem 3; pixel_out <= incoming_pixel ; end if ; end if ; end process reading_from_file ;
As said, do multiple reads per line.
Code:readline ( my_file , current_line ) ; read ( current_line , incoming_pixel1 ) ; read ( current_line , incoming_pixel2 ) ; read ( current_line , incoming_pixel3 ) ;
You won't need to ask if you reviewed the description of textio package in VHDL LRM.
reading_from_file : process ( reset , clock ) is
file text_file : text open read_mode is "C:\some_location\some_file.txt" ;
variable current_line : line ;
variable pixel : integer ;
variable pixel_counter : integer := 0 ;
variable valid_data : std_logic := '0' ;
begin
if reset = '1' then
valid_data := '0' ;
valid_data_out <= valid_data ;
elsif rising_edge ( clock ) then
if ( not endfile ( text_file ) ) then
valid_data := '1' ;
valid_data_out <= valid_data ;
if pixel_counter = 0 then
readline ( text_file , current_line ) ;
end if;
read ( current_line , pixel ) ;
pixel_counter := ( pixel_counter + 1 ) rem 3 ;
pixel_out <= std_logic_vector ( to_signed ( pixel , pixel ' length ) ) ;
else
valid_data := '0' ;
valid_data_out <= valid_data ;
end if ;
end if ;
end process reading_from_file ;
reading_from_file : process ( reset , clock ) is
file text_file : text open read_mode is "C:\some_location\some_file.txt" ;
variable current_line : line ;
variable pixel : integer ;
variable pixel_counter : integer := 0 ;
variable valid_data : std_logic := '0' ;
begin
if reset = '1' then
valid_data := '0' ;
valid_data_out <= valid_data ;
elsif ( not endfile ( text_file ) ) then
if rising_edge ( clock ) then
valid_data := '1' ;
valid_data_out <= valid_data ;
if pixel_counter = 0 then
readline ( text_file , current_line ) ;
end if;
read ( current_line , pixel ) ;
pixel_counter := ( pixel_counter + 1 ) rem 3 ;
pixel_out <= pixel ;
end if ;
else
valid_data := '0' ;
valid_data_out <= valid_data ;
end if ;
end process reading_from_file ;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 variable good : boolean; variable l : line; ....... read(l, ip, good); if not good then -- do something because the line ended end if;
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