These are the important lines:
Source: u_digi/u_async/u_ht80c51/i_oci_VAR_reg__3_m0/r_e_g11_1 (FF)
Destination: u_digi/u_async/u_ht80c51/i_core_c6817_s_0_qn_m0/r_e_g31 (FF)
Requirement: 10.000ns
Data Path Delay: 9.969ns (Levels of Logic = 10)
You have 10ns available, but the ten levels of combinatorial logic between those two flops are causing almost 10ns of delay. Plus a few more picoseconds due to the imperfect clock, and your timing budget is exceeded, slightly.
Examine the design to see why it has so many levels of logic. If the design allows it, consider adding pipelining to reduce the number of logic levels. That would make a tremendous improvement in speed.
Search your ISE "Development System Reference Guide" for the words "closure", "effort", and "strategy", and you'll find various options for improving optimization. A good one to try first is "timing driven packing".
Also read the "Design Considerations" chapter in your "Synthesis and Simulation Design Guide". It describes various helpful techniques.