Delay will probably be a wash (w/ width) on wide busses because plate
capacitance goes up while resistance goes down. But this has some
nuances when you get to thinner traces closely spaced because fringing
C can match or exceed plate C. Whether you'd see this in post-layout
parasitics depends on how diligent the PDK developers were, in how they
figure trace capacitances. Separation reduces line-line but not line-substrate C.
A layer higher in the stack will have trivial plate and dominant fringing
capacitances, and respond most to spacing.