So, may I know, what I can do now to solve the problems? Because I still blur about it. These few days, I try to use the standard cells inside the Mentor Graphics to build the ALU, unfortunately, I only manage to run the simulation until 4-bit ALU. The simulation of 8-bit ALU still cannot get the waveform.This is only speculation... You appear to have several stages where a later stage has some of its inputs undefined, until an earlier stage generates a definite output. This is not an error (electrically speaking), however as for the robot-like simulator it has to start a run with undefined states at several inputs. (Similar to floating inputs.) Therefore it has trouble achieving convergence during the first few iterations.
We'd expect such a situation to have a workaround built into the simulator's algorithms, so it doesn't get bogged down by such a simple thing. And maybe it does contain safeguards...
But just in case your schematic causes difficulty, it might help if you were to install pull-up (or pulldown) resistors at inputs that appear undefined at the start of a run.
Noted, I will look into it.You might want to look at acquiring veriloga
logic gate models (like from Ken Kundert's web
pages - designers-guide.org ?) and use them
as a stepping-stone to validate your higher
level assembly with efficient simulation, then
substitute transistor level versions.
Of course you'd need a simulator than will
digest veriloga, which is not many of the open
source ones. I'd expect Mentor and know Cadence
to be capable (some assembly required, the veriloga
code has to be fitted up to symbols and so on).
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