You mentioned Project Navigator, so I assume you are referring to a modern Xilinx FPGA. The Block RAM is a friendly synchronous device that uses the positive clock edge. It behaves like a big register array, although the clock-to-output delay is usually slower than a slice flop. In most projects you don't have to worry much about the block RAM's precise timing details, but if you need them see the "switching characteristics" section of the FPGA data sheet.
Some Xilinx FPGAs provide special Block RAM features such as an optional output register that improves the clock-to-output delay. Read about the various features in your specific FPGA User Guide.