Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Memory Limitations of FPGA

Status
Not open for further replies.

win2010

Member level 1
Joined
Sep 30, 2010
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,605
Hi......................

I`ve files which are contain plenty addresses(integers 16-bit). Each file contain lakh together integers. I need to store and used in a program.
I`m worry about memory of FPGA whether which sufficient or not. Because each and every model has many memory blocks used i.e. RAM/ROM. After integrating all block there is no such issues which in large to store or like that. I used spartan 3A DSP.

What mearure should take before if it occure in future....?
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,000
Helped
2,056
Reputation
4,129
Reaction score
2,006
Trophy points
1,393
Activity points
38,416
I dont understand the question. FPGAs have lots of small memories. If you dont use them efficiently they get wasted. It is not like the memory on a PC.
 

win2010

Member level 1
Joined
Sep 30, 2010
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,605
I have lots of files to store then How effectively we can use the FPGA memory....I`m asking this
 

pbernardi

Full Member level 2
Joined
Nov 21, 2013
Messages
129
Helped
27
Reputation
54
Reaction score
27
Trophy points
28
Activity points
988
In verilog, you can use $readmemh:

initial $readmemh("pathtofile", memoryname);
Please note that your file must be exactly on the same size of your memory. For example:

reg [31:0] RAM [0:511];
initial $readmemh("C:/RAM.dat", RAM);
I use the file in HEX format, with the exact numbers of entries the memory needs. In example above, you would need a file with 512x32 bytes entries (e.g. FFFFFFFF). I am not sure if others formats are accepted, I always used like this.

Of course, you need a block inferred/explicit block RAM for this procedure. I have never tested this in distributed RAM.
 

shahulakthar

Member level 2
Joined
Oct 13, 2009
Messages
45
Helped
12
Reputation
24
Reaction score
10
Trophy points
1,288
Location
Chennai, India
Activity points
1,515
I have lots of files to store then How effectively we can use the FPGA memory....I`m asking this
If you want to store lot data in to Spartan series FPGA it is not possible. Another way you can store data with your FPGA is using External memory Such us SRAM, DDR, Flash.

You can use IP core from Xilinx Patform Studio tool to interface with Memory to Processor and store data in it. program it to FPGA.

For that You require board similar to this with external memory

Spartan-3 EDK Kit


Regards,
Shahul
 

win2010

Member level 1
Joined
Sep 30, 2010
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,605
Thant you for replay.....

We have constraint on memory How can i come to know this much only FPGA going to store.....?
Is there any particular method to know....?
 

rberek

Full Member level 6
Joined
May 23, 2007
Messages
339
Helped
98
Reputation
202
Reaction score
83
Trophy points
1,308
Location
Canada
Activity points
3,768
How can i come to know this much only FPGA going to store.....?
By reading the FPGA's datasheet. Al lthe information about the FPGA is listed there.

r.b.
 

shahulakthar

Member level 2
Joined
Oct 13, 2009
Messages
45
Helped
12
Reputation
24
Reaction score
10
Trophy points
1,288
Location
Chennai, India
Activity points
1,515
Thant you for replay.....

We have constraint on memory How can i come to know this much only FPGA going to store.....?
Is there any particular method to know....?
FPGA consist of 2 types of memory.
1.Block RAM
2.Distributed RAM

Check Datasheet for its size.
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834
Thant you for replay.....

We have constraint on memory How can i come to know this much only FPGA going to store.....?
Is there any particular method to know....?

you can store the data in bram and reuse the bram multiple number of times...however in this case you cannot pipeline or do parallel processing...this may increase the delay of the algorithm so there is a trade off..
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,000
Helped
2,056
Reputation
4,129
Reaction score
2,006
Trophy points
1,393
Activity points
38,416
you can store the data in bram and reuse the bram multiple number of times...however in this case you cannot pipeline or do parallel processing...this may increase the delay of the algorithm so there is a trade off..
Usually the higher latency means you get a higher data throughput. This is far more important for FPGAs.
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834
if you are dealing with large chunks of source data latency is expected...
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,000
Helped
2,056
Reputation
4,129
Reaction score
2,006
Trophy points
1,393
Activity points
38,416
if you are dealing with large chunks of source data latency is expected...
This is rather vague, and doesnt really mean anything.
You may have a large dataset, but you may parrellise your algorithm to process it all in parrell. But this may not be possible. It depends on the data and situation.
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834
you cannot store a data in parallel processing..in parallel processing once the data has been used up....when I say large chunks of data it definitely is not just a bit size data....of course it depends on the data and situation but like i said you have latency because its just not a bit size data..
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,000
Helped
2,056
Reputation
4,129
Reaction score
2,006
Trophy points
1,393
Activity points
38,416
you cannot store a data in parallel processing..in parallel processing once the data has been used up....when I say large chunks of data it definitely is not just a bit size data....of course it depends on the data and situation but like i said you have latency because its just not a bit size data..
What? I store plenty of data in my parrallel processing. Im usually processing pixels of data in real time video....
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834
there is a reason why real time video is limited only to PC or large memory systems because machine learning algorithms need video data samples which helps in the classification process so fpga is not suited for such kinda algo's
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,000
Helped
2,056
Reputation
4,129
Reaction score
2,006
Trophy points
1,393
Activity points
38,416
Are you joking? There are plenty of people doing real time video processing on video with very small FPGAs. A 2d FIR can be done on real time video with 2 line latency for example inside an FPGA. It can be done on an FPGA costing about less than $100.

How do you think TV companies compress their video streams for live transmission?
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834
hi...2D FIR is a very basic algorithm and yes you do not need resuing bram or in fact u do not need bram...u just need a 2 line buffer like you have mentioned..but however requirement has been changed and people do much more complicated algo's than just the 2D FIR...by the way machine learning algo's are much more complex and they are database based...the algo which you are talking about is just a basic image processing algo..
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,000
Helped
2,056
Reputation
4,129
Reaction score
2,006
Trophy points
1,393
Activity points
38,416
Then why did you say real time video is limited to PC with large memory?

Yes, FPGA is not suited to all algorithms, but this thread isnt about that....
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834
i never started the real video topic.you started it.you said you are processing real time video...what i was saying was that memory has a trade off and u need to have more than 100$ boards to process bigger memories and to try out fancy algo's than 2D FIR...
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
hi...2D FIR is a very basic algorithm and yes you do not need resuing bram or in fact u do not need bram...u just need a 2 line buffer like you have mentioned..but however requirement has been changed and people do much more complicated algo's than just the 2D FIR...by the way machine learning algo's are much more complex and they are database based...the algo which you are talking about is just a basic image processing algo..
Well damn. I guess that means my non-database related multilayer perceptron doesn't work in this here spartan-6...
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top