Memory Layout Question

[santhosh.vlsi]

Hi all,

Anyone can please provide me the details about the memory layout engineer responsibilities in the semiconductor companies.

 

[erikl]

... memory layout engineer responsibilities ...

You should

• understand silicon layout methodology and tools
  
• understand the architectures of the memories
  
• understand the physical and electrical significance of any layout structure
  
• understand all the involved mechanisms of memory data write, conserve and read back, as well as provisions to sustain and read back data correctly (refreshing, rewriting)
  
• understand the function of the analog read comparator and its temperature dependent readjustment
  
• know your foundry's / fab's technology capabilities
  
• understand the backend processes and be capable to cooperate with the backend guys
  
• have ideas about using these process capabilities in order to save silicon area resp. improving the yield
  
• know and understand your competitors' architectures and layouts

 

[santhosh.vlsi]

Thank You Mr.erikl

As per my knowledge technology node means it depends on the gate length of the transistor.Suppose i want to design a memory block in 22nm node, What points i want to consider.Any text books enriches these aspects with EDA tool examples.


Thank you

 

[erikl]

Suppose i want to design a memory block in 22nm node, What points i want to consider.

The peculiarities of the process used. Deep trench capability.

Any text books enriches these aspects with EDA tool examples.

Don't know of any text book on 22nm memory. But you can G00GLE a lot on this.