rafimiet
Member level 5
For Altera we use the following to initialize the memory
type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram :
signal is "my_init_file.mif";
However, for xilinx we have .coe files for initialization rather than .mif
I have created the coefficient file in .coe format, now I need to access that in the main code for memory. How can I do that in xilinx using VHDL?
type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram :
signal is "my_init_file.mif";
However, for xilinx we have .coe files for initialization rather than .mif
I have created the coefficient file in .coe format, now I need to access that in the main code for memory. How can I do that in xilinx using VHDL?