Meet vivado error in the bitgen phase

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flypig

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I meet one ViVADO error,
ERROR:[Drc 23-20] Rule violation (PDRC-133) SLICE_PairEqSame_B6B5_ERROR- Incompatible programming for SLICE_X283Y355. B6LUT and B5LUT must have a compatible equation,lower bits must be programmed the same.

It is so strange for me?

Anyone find the solution about it?:?:
 

I have also experienced this error. It happens during the final DRC before the bit file is generated. I am using Vivado 2013.1 targeting a K7 325 FFG900, did anyone ever figure this one out?

My design meets timing and is using two Xilinx cores, one of them is the purchased Tri-Mode Ethernet MAC core.
 

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