Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Measuring the Edge Rate in logic circuits

Status
Not open for further replies.
P

ParkerMike

Guest
Newbie level 1
How do you measure the Edge Rate in logic circuits?
What kind of circuits would you want to measure the Logic Edge rate?
 

Edge rates are often limited by the source resistance and load capacitance. Thresholds for switching states will change with temperature and there are many other considerations, but prop. Delay is important and rise & fall times are specified with worst case and typical due to these considerations.

Logic is usually single ended. But using comparators with differential inputs allows the user to define switching thresholds. Slow rising edges often have ripple and need Schmitt trigger inputs to "square up" the edges.

There are many methods used to measure rise and fall time, due to many different thresholds used for requirements. 10-90% is common for many signals, as is 30-70% or just the slew rate , when determined by drive current limit and load capacitance.
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top