Measuring efficiency of a buck converter

[analog_match]

Hi All,

Can anyone tell me given a sync buck converter with certain FETs, certain L's and C's and a certain gate driver, what should my experimental setup be to measure efficiency. Also how do I characterize/measure switching losses including reverse recovery losses v/s conduction loss?

Thanks

 

[dick_freebird]

The simplest efficiency measure is "wallplug" efficiency -
(IOUT*VOUT)/(IIN*VIN). Also the most relevant to the user.

Vendors of components like to de-embed the losses from any
component they didn't make. You'll see this kind of fancy
footwork in IC datasheets.

As a designer, you'd want to know more. One of our guys on
my DC-DC development team is really good at modeling
and has an Excel sheet that's populated bottom-up with all
of the inefficiency (loss) terms we've been able to think of.
Upper and lower FET on resistance, interconnect resistance,
gate charge (times frequency), even external component
losses (which can be a bigger deal than you might think,
we're seeing several percent just in the VIN decoupling
caps' ESR).

Can't share that with you, other than the basic idea.

You should not have reverse recovery losses in a sync buck
unless your timing is so sloppy that you let the LSS go "upside
down". But if you do, just take your negative voltage
pedestal (from the 'scope) times its duration times the output
current, and there's a Joule slug for you on every cycle
(a switching-loss term).

 

[analog_match]

Hello dick_freebird,

Thanks for your reply.

Regarding your comment on reverse recovery, even in a sync buck, when the freewheeling body diode of the LSS which is conducting during the dead time starts going OFF as switch node rises, the additional current it pulls will appear as a spike in the HSS which now having some higher voltage across it will be an additional loss correct? Will this not be a significant loss? Your feedback will be valuable as I am still learning and trying to get a feel for these concepts.

Thanks

 

[dick_freebird]

You'd like the LSS to catch the falling edge just before,
or as it crosses ground so that the body diode never gets
to conduct. That's going to be tough to control well, without
a zero-crossing servo loop (to take out FET gate drive
timing variation).

The FET could be backstopped with a Schottky or you could
look for FETs that have a low spec'd Trr, if you don't have
a control scheme that can keep the FET reliably away from
reverse conduction.

HSS drain voltage spiking only costs you Qdd per cycle, if
the HSS is off.

LSS diode you'd hope would cease conduction before
the next L-H transition, but if you push frequency or duty
cycle to where you have a low-side on time less than Trr,
you will push the whole stored junction charge from VIN
into GND. Presuming the LSS on resistance was unable to
quench the body diode. In any case the body charge will
be wasted, either from VIN or from the freewheel current.

Long story short, "don't go there", by whatever it takes.

 

[FvM]

Refering to your original question, it's not easy to measure the different loss contributions exactly. A simulation is often
the better way to see the detail effects.