recently , i'm designing a pipelined adc with matlab simulink?
but there are some questions:
1 how to built per stage(1.5bit) use the method of transfer function?
2 how to measure the snr sndr sfdr enob inl dnl in simulink,and how to plot the in matlab?
3 if i take kt/c into acount,then what does "c" means ?the sampling cap or the total cap of per stage (if so,how to measure it)?
Hi,
You can build the 1.5 bit stage with either sub-blocks like comparator and logic gates for sub-dac, or by writing the necessary functions in a m-file ("Embeded matlab function" block in simulink).
After you build the systematic ADC in simulink you can either export the output data to a variable in MATLAB (there is a block simulink to do this) or you can export the data in the scope (the scope you have at the output) to MATLAB workspace. Then you should write a program to calculate the parameters you need.
For exact noise calculation you can see "Cho" thesis.
I will upload the thesis later (I can't upload it now).
dear sir, I saw your adc model and found it useful. could you please guide me how can i find out INL and DNL and all other parameters to see adc's performance in simulink( or other way) and after that i can apply digital calibration on that.