[SOLVED] meaning of this verilog syntax??????????

[anirbanphys]

Hi all,

what is the meaning of this one in the specify block?

specify
$recovery(posedge preset &&& (reset !== 1'b1), posedge clear &&& (reset !== 1'b1) ,1, note);
endspecify

 

[kornukhin]

$recovery (reference_event, data_event, limit, [notifier]);

reference_event - the transition at a ontrol signal that establishes the reference time for tracking timing violations on the data_event.
data_event - the signal change that initiates the timing check and is monitored the violations.
limit - a time limit used to detect timing violations on the data_event.
notifier - an optional argument that "notifies" the simulator when a timing violation occurs.

In your case this timing check sets 1 time unit delay check between posedge clear and posedge preset signals (at the same time reset should not be equal to 1).