meaning of spddiv speeddiv (.dividend (32'd1200...

[Vimalab]

spddiv speeddiv(.dividend(32'd12000000),.divisor(tcount),.quot(quot).....);

what is the meaning of above statement? why we are using this statement in verilog code?

 

[ads-ee]

Looks like a divider core is instantiated in the design.

Based on this and your previous question you should read a book on Verilog. Maybe you have a software background a felt you could pick up Verilog by looking at examples. Verilog doesn't behave like a software program as there is concurency. If you don't learn the language from a book or the LRM you'll end up learning the language after endless painful mistakes.

Regards