Layout Generation Tools
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Compactors
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A Compactor can be used at almost all level of layout Complexity. Most of them are best used at a transistor or cell level. The tool is used to compact transistor layout and their connections inside a cell design.
One approach to using this type of tool is for the layout designer to do a loose job and run the compactor to optimize the layout. This is very fast and efficient methodology to generate DRC clean layout cells.
For cell-level layout, the setup and maintenance of a compactor requires a very knowledgeable designer. The advanced compactors that are available today, together with schematic or netlist-driven layout generators, can provide the best of all worlds because the result is correct by construction and should pass both DRC and LVS checks. In the case where the compactor works on symbolic layout data, the results are extremely fast, and they can add advanced structures such as jogs within a wire if required.