Re: May a CPLD have 3 clock input? these clock is not releva
Thank u, sir.
I tried this module, in MaxPlus. there is no compile error. but there are limit of assign clk1, clk2, clk3 pins. some pin can be used as normal input, but can not be used as clock input. improper pin assignment cause fit errors.
module test ( clk1, clk2, clk3, count );
input clk1, clk2, clk3;
output[3:0] count;
reg [3:0] count1;
reg [3:0] count2;
reg [3:0] count3;
always@( posedge clk1 )
count1 = count1 + 1;
always@( posedge clk2 )
count2 = count2 + 1;
always@( posedge clk3 )
count3 = count3 + 1;
assign count = count1 + count2 + count3;
endmodule