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Devices operating with the conventional standard SPI need pull-up resistors, which makes the bus somewhat "weak". For frequencies above the MHz order, must consider use an electrical standards based on differential pairs.
The original SPI specification has been issued by Motorola and doesn't use any open drain signals. Instead MISO (slave data out) has tristated push-pull drivers, the other (master driven) signals are permanently enabled push-pull. Open drain with pull-up is used in some SPI alike variants, but isn't genuine SPI technique.
Recent fast SPI devices with 50 MHz and higher clock frequency are using a CMOS I/O standard, mostly 3.3V. The bus extension is of course limited with highest speeds, but a few 10 cm can be achieved with suitable design, e.g. using source-side series termination. Differential signalling, as mentioned by andre_teprom, can extend SPI range to many meters, mainly limited by cable and tranceiver delay and respective round-trip time.
As all SPI lines are driven by totem-pole drivers you don't need pullups on any of the lines.
Also there was never any lower limit frequency specification given for SPI back in the old 68HC microcontroller days. Even the current versions of the part don't specify any lower limit frequency. AFAIK you could run the SPI at 1 Hz.
The maximum frequency is not defined either, except for each individual part. If I recall correctly the original SPI was run a 1 MHz but that wasn't defined by any specification just the documentation for the interface in the part it was used in. You could run SPI at 1 GHz if you could manage the signal integrity and the problems with having to use the SPI clock to run the interface (You probably don't want to try and oversample a 1 GHz SPI interface like most designs do).