when i sad counter i mean integer counter.
actually i dont need a clock that much fast . but during the operation the source signal phase(500Mhz) may be shift. when i use the source for trigger, i can adjust the time for driving components.
in brief,
the algorithm may be like this,
process (clc)
begin;
if rising_edge(clc) then
counter<=counter+1;
if counter=1 then
output<='1';
end if;
if counter=10000 then
output<='0';
end if;
if counter=20000 then
counter<=0;
end if;
end if;
end process;
the number 10000 -20000 isnt exact(just an example). im not sure it know, it will be biger than it is now.