maximum clock operation

[yburake]

hi,

i have xilinx spartan 3e-100 cp132 fpga board
.

its datasheet says it can handle 500Mhz+ operations.
but i tried in 256 MHz operation it cannot hand it(the operation is just counting). i searched in online fpga boards, most of boards datasheet says they can handle 500mhz. how can i trust the datasheets, can anyone knows a board that can really handle 500Mhz?

Regards
Burak

 

[TrickyDicky]

That figure will the ideal maximum - if all LEs were placed connected to a single register routed to the adjacent LE.

In reality it is going to depend hevily on your design. So it is best to ignore theoretical maximum and just see what you can squeeze out of your design.

 

[alexan_e]

The MAX frequency will be different for each code implementation, it is reported from the vendor tool after fitting.
What kind of counter did you use, how many bits?

Alex

 

[shanmugaveld]

The acheivable frequency is mostly depends on the logic what you are using.

 

[yburake]

when i sad counter i mean integer counter.
actually i dont need a clock that much fast . but during the operation the source signal phase(500Mhz) may be shift. when i use the source for trigger, i can adjust the time for driving components.
in brief,

the algorithm may be like this,

process (clc)
begin;

if rising_edge(clc) then
counter<=counter+1;

if counter=1 then
output<='1';
end if;

if counter=10000 then
output<='0';
end if;

if counter=20000 then
counter<=0;
end if;

end if;

end process;

the number 10000 -20000 isnt exact(just an example). im not sure it know, it will be biger than it is now.

 

[TrickyDicky]

An integer counter is 32 bits for a start, so a counter is spread over 32 LEs (for the +1) and 32 registers.
Secondly - logic generated clocks is a bad bad idea. Use clock enables instead.