Maximize the beta of bipolar transistor in CMOS technology

Status
Not open for further replies.
N

neoflash

Advanced Member level 1
Joined
Jul 2, 2005
Messages
492
Helped
10
Reputation
20
Reaction score
2
Trophy points
1,298
Activity points
4,759
β of the planar bipolar transistors is a big headache of the modern CMOS technology.

Accoring to the principle theory, β is a function of base area width. Is there any paper/book report any tricks for maximizing the β with layout optimization?
 

In std. CMOS technologies you just have vertical pnp transistors available, and the base width is the difference between n-well depth and S/D p+ implant junction depth, i.e. only process dependent, not manipulable by design.

Dedicated analog CMOS technologies also allow for lateral BJTs, but here the base width is limited by design rules, enabling higher, but still limited beta.

To do even better, you'd need your own CMOS tech., or at least the permission to intelligently circumvent the design rules ;-)
 

    N

    neoflash

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…