max current in different layer at 45 nm process

[john7796]

current carrying capacity in different layer at 45 nm process

Hi All,

I estimate one plan now.

Ｉ need current carrying capacity in M1 M2 M3 M4 with 140nm width metal line at 45 nm process.

Could any one help me ?

Thanks.

John

 

[dick_freebird]

You need a lot more info & analysis.

Each layer's minimum thickness needs to be declared. This
ought to include step coverage (thickness reduction over
worst case topography).

Similarly the 140nm could easily come out narrower in
spots (notching) or locally (field loading) or globally
(litho tolerances).

If you're conservative then you would worst-case both
to arrive at a minimum cross sectional area.

Now, your "peak" current - is it balanced and reversing,
like a wire driving a capacitive load? Or unidirectional?
Reversing, reverses most electromigration and you can
apply a higher current density rule. Unidirectional, you
get to time-average it and apply DC reliability rules.
This then means you need to assert a pulse frequency.
If you don't know it then again you get to assume the
worst.

Then, you want to know the metallization temperature
as this is a strong wearout accelerator. The use-temp will
factor into the allowable current density for the modes, that
you would calculate from current and the sandbagged CSA.

All of this ought to have been done already and be in the
process design kit docs, or available on request from the
foundry (if they think you are a customer - lookie-loos
don't get so much love, you could be a competitor in
disguise).

 

[john7796]

Thank you. But I can't get process design kit docs, so could you help me ?

I need current carrying capacity in M1 M2 M3 M4 with 140nm width metal line at 45 nm process.

 

[erikl]

Here's a conservative estimation for the 45nm process: 0.35µA/µm for the lower metals, 0.7µA/µm (of width) for the top metal.