we need to set the fanout & tran limit in our SDC file.
In 130nm designs, we were setting the fanout & tran as "1"
But need to come up with these numbers for 65nm designs.
What is the general procedure for coming up for this number?What do people normllay set max cap & max tran limit in their sdc files for 65 nm designs.
yes, for normal case, library setting can meet your request such as fanout&tran. but for some special case you need to set your own constraints (more strict than the library setting) such as clock tree path.